//will tested with FPGA Advantage


// this is a test for pn code "Uplink"

module test5(data_out, clk, reset);
  
output data_out;
input clk, reset;

reg [24:0] a, b;                       // a is the upper register
                                             // b is the lower register
reg c, d, f;                             // c is the upper feedback
                                            // d is the lower feedback
                                            // f is the output entering the mapper


always @ (posedge clk)
if (!reset)
begin
a = 25'b1_1111_1111_1111_1111_1111_1111;
b = 25'b1_1111_1111_1111_1111_1111_1111;
c = 1'b0; 
d = 1'b0;
f = 1'b0;
end
else
begin

f = a[0] ^ b[0];

c = a[0] ^ a[3];
a = {c ,a[24:1]} ; 

d = b[0] ^ b[1] ^ b[2] ^ b[3];
b= {d, b[24:1]} ;  


end 
assign data_out = f;
endmodule