// Defining Instructions opcodes
`define ADD	   3'd0
`define ADDI	   3'd1
`define NAND	   3'd2
`define LUI	   3'd3
`define SW	   3'd4
`define LW	   3'd5
`define BEQ	   3'd6
`define JALR	   3'd7


module superscalar (clk,reset,en,out_data);
input clk, reset, en;
output out_data;

reg out_data;
reg [7:0]pc ; //program counter register
reg [3:0]ff ; //Fetch flag check
reg [47:0]fb1,fb2,fb3,fb4 ; //four Fetch buffers or pipelining 
reg [15:0]IM[255:0] ; //Instruction Memory
reg [3:0] stall ; // Stalling process register that indicate //that four Fetch buffers are full
reg waiting ; //Waiting signal
reg zero ;
reg bus_check_even,bus_check_odd;
reg fetch_dog;
reg [1:0] p;

//this is the reset part of the first phase
always @(posedge clk)
begin
  if (en) //Processor enable
    begin
      if (!reset)
        begin // reset all vectors
        pc = 8'b0 ;
        ff = 4'b0 ;
        fb1 = 48'b0 ; fb2 = 48'b0 ; fb3 = 48'b0 ; fb4 = 48'b0 ;
        stall = 4'b0 ;
        waiting = 1'b0 ;
        p=2'd0;
        //Memory test here memory is filled by the dirty method
        IM[0] = 16'b0001110010000010 ;
        IM[1] = 16'b0000000000000000 ;
        IM[2] = 16'b1111111111111111 ;
        IM[3] = 16'b0000000000000000 ;
        IM[4] = 16'b0000000000000000 ;
        IM[5] = 16'b0000000000000000 ;
        IM[6] = 16'b0000000000000000 ;
        IM[7] = 16'b0000000000000000 ;
        IM[8] = 16'b0000000000000000 ;
      end
    else



//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//Fetch Phase (start)/////////////////////////////////////////
/////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////
//fetch flag check to transfer instruction from IM to fetch buffer 
//(start) 
      begin
      case(p) 
        
       2'b00:
       begin
        if (!ff[0])
          begin
            fb1 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
            ff[0] =   1'b1 ; // Processor can't write in fb1 //untill the data inside it is used before
            pc = pc + 8'd2 ; // update program counter
          end
        else if (!ff[1])
          begin
            fb2 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
            ff[1] =  1'b1 ; // Processor can't write in fb2 untill the data inside it is used before 
            pc = pc + 8'd2 ; // update program counter
          end
        else if (!ff[2])
          begin
            fb3 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
            ff[2] =  1'b1 ; // Processor can't write in fb3 //untill the data inside it is used before
            pc = pc + 8'd2 ; // update program counter
          end
         else if (!ff[3])
           begin
            fb4 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
            ff[3] =  1'b1 ; // Processor can't write in fb4 //untill the data inside it is used before
            pc = pc + 8'd2 ; // update program counter
           end
         else
           begin
           stall = stall + 4'd1 ;
           p=p+2'b01;
           end  
          end
        
         2'b01:
         begin
          if (!ff[1])
            begin
              fb2 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
              ff[1] =  1'b1 ; // Processor can't write in fb2 //untill the data inside it is used before 
              pc = pc + 8'd2 ; // update program counter
            end
          else if (!ff[2])
            begin
              fb3 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
              ff[2] =  1'b1 ; // Processor can't write in fb3 //untill the data inside it is used before
              pc = pc + 8'd2 ; // update program counter
            end
           else if (!ff[3])
             begin
              fb4 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
              ff[3] =  1'b1 ; // Processor can't write in fb4 //untill the data inside it is used before
              pc = pc + 8'd2 ; // update program counter
             end
           else
             begin
             stall = stall + 4'd1 ;
             p=p+2'b01;
             end
            end
          2'b10:
          begin
           if (!ff[2])
             begin
               fb3 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
               ff[2] =  1'b1 ; // Processor can't write in fb3 //untill the data inside it is used before
               pc = pc + 8'd2 ; // update program counter
             end
            else if (!ff[3])
              begin
               fb4 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
               ff[3] =  1'b1 ; // Processor can't write in fb4 //untill the data inside it is used before
               pc = pc + 8'd2 ; // update program counter
              end
            else
              begin
              stall = stall + 4'd1 ;
              p=p+2'd1;
             end
             end
           2'b11:
           begin
            if (!ff[3])
               begin
                fb4 = {IM[pc], pc, IM[pc+8'b1],pc+8'b1};
                ff[3] =  1'b1 ; // Processor can't write in fb4 //untill the data inside it is used before
                pc = pc + 8'd2 ; // update program counter
               end
             else
               begin
               stall = stall + 4'd1 ;
               p=2'd0;
             end
             end
             endcase
       end
     end
//fetch flag check to transfer instruction from IM to fetch buffer (end)
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//Fetch phase (end)///////////////////////////////////////////
/////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////
      else // if not enable turn on waiting LED
        waiting = 1'b1 ;
      end
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//Enqeue Phase (start)////////////////////////////////////////
/////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////    
//Register File construction 
reg [15:0]reg_file[7:0] ; //Register file Memory
reg [15:0]reg_file_out1, reg_file_out2, reg_file_out3, reg_file_out4; //Register file output without ID
reg [2:0]ID_A, ID_B, ID_C ; //ID temp Buffers 
reg reg_file_flag[7:0] ; //Register for check if file register need or have ID or not
reg [2:0]rA ; //Target address
reg [2:0]rB ; //First source address
reg [2:0]rC ; //Second source address
reg [2:0]op ; //Opcode register
reg [6:0]imm ; //Immediate register for special commands
reg [9:0]extend_imm ; //Extend immediate register
reg [61:0]enqu_bus_buff_even, enqu_bus_buff_odd ; //Enqeue Bus //buffers
reg enqu_bus_buff_flag_even, enqu_bus_buff_flag_odd ; //This flags //check if Enqeue Bus busy or not 
reg [3:0]space ; //General purpose register
reg [15:0]src_operand ; //Used in SW Instruction
reg [15:0]branch_count_cntl ; //Used in BEQ instruction

integer i ;    

//processing data between Fetch buffers and Register File
always @(posedge clk)
begin
if (en) //Processor Enable
  begin
    if (!reset)
      begin //Initialize all vectors here as follow
        for (i=0 ; i<8 ;i = i + 1)
         begin
          reg_file_flag [i] = 1'b0 ;
         end
         space = 4'b0 ;
         enqu_bus_buff_flag_even = 1'b0 ;
         enqu_bus_buff_flag_odd = 1'b0 ;
         // to be removed 
         reg_file [1]=16'b0000000000000001;
         reg_file [2]=16'b0000000000000010;
         // not to be removed 
      end

//Check Fetch buffers and take its contant if it ready
    else if (ff[0])
      begin
/////////////////////////////////////////////////////
//For the first half of the first Fetch buffer//////
///////////////////////////////////////////////////
      begin
        {op, rA} = fb1[47:42] ;//Fixed part in all instructions //of the first part of FB1
        case(op)
//ADD Instruction in Enqueue Phase
          3'b000: begin
                   {rB, space, rC} = fb1[41:32];//This part is //differ from instruction to other 
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = 3'b0 ;
                     end
                    else
                     begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                     end
                   end
               
                  if (!reg_file_flag[rC])
                   begin
                    reg_file_out2 = reg_file[rC] ;
                    ID_C = 3'b0 ;
                   end
                  else
                   begin
                    reg_file_out2 = reg_file[rC] ;
                    ID_C = rC ;
                   end
                   enqu_bus_buff_even = {fb1[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
                  end
//ADDI Instruction in Enqueue Phase
          3'b001: begin
                   {rB, imm} = fb1[41:32] ;//This part is differ //from instruction to other  
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                   end
                   ID_C = 3'b0 ;   
                   reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                   enqu_bus_buff_even = {fb1[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;                                      
                   end
//NAND Instruction in Enqueue Phase
          3'b010: begin
                    {rB, space, rC} = fb1[41:32] ;//This part is differ from instruction to other 
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                   end
                
                   if (!reg_file_flag[rC])
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = rC ;
                    end
                   enqu_bus_buff_even = {fb1[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
                  end
//LUI Instruction in Enqueue Phase
          3'b011: begin
                   extend_imm = fb1[41:32] ;
                   ID_B = 3'b0 ;
                   ID_C = 3'b0 ;
                   reg_file_out1 = {extend_imm, 6'b0} ;
                   enqu_bus_buff_even = {fb1[47:24], reg_file_out1, ID_B, 16'b0, ID_C} ;//Note that we discard the value of //reg_file_out2
//The even bus now is busy with the recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
                  end





//LW Instruction in Enqueue Phase 
          3'b100: begin
                   {rB, imm} = fb1[41:32] ;//This part is differ from instruction to other  
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                   end
                   ID_C = 3'b0 ;   
                   reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                   enqu_bus_buff_even = {fb1[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
                  end
//SW Instruction in Enqueue Phase 
            3'b101: begin
                     {rB, imm} = fb1[41:32] ;//This part is differ from instruction to other  
                     begin
                       if (!reg_file_flag[rA])
                        begin
                         reg_file_out2 = reg_file[rA] ;
                         ID_A = 3'b0 ;
                        end
                       else
                        begin
                         reg_file_out2 = reg_file[rA] ;
                         ID_A = rA ;
                        end
                      if (!reg_file_flag[rB])
                       begin
                        reg_file_out1 = reg_file[rB] ;
                        ID_B = 3'b0 ;
                       end
                      else
                       begin
                        reg_file_out1 = reg_file[rB] ;
                        ID_B = rB ;
                       end
                     end
                     ID_C = 3'b0 ;
                     reg_file_out2 = reg_file[rA] ;   
                     src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                     enqu_bus_buff_even = {fb1[47:24],reg_file_out1, ID_B, src_operand, ID_A} ;//The even bus now is busy with the //recent instruction so we do the following
                     enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;  
                    end
//BEQ Instruction in Enqueue Phase 
          3'b110: begin
                    {rB, imm} = fb1[41:32] ;//This part is differ from instruction to other
                    if (!reg_file_flag[rA])
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = rA ;
                     end
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                    end
                   ID_C = 3'b0 ;
                   branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
                   enqu_bus_buff_even = {fb1[47:24],reg_file_out1, ID_B, reg_file_out2, ID_A} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
                  end
//JALR Instruction in Enqueue Phase 
          3'b111: begin
                   {rB, imm} = fb1[41:32] ;//This part is differ //from instruction to other 
                   if (!reg_file_flag[rB])
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                    end
                   ID_C = 3'b0 ;
                   reg_file_out2 = 16'b0 ;
                   enqu_bus_buff_even = {fb1[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;
                  end
        endcase
      end



////////////////////////////////////////////////////////////
//for Second half of first Fetch buffer////////////////////
//////////////////////////////////////////////////////////
       begin
         {op, rA} = fb1[23:18] ; //Fixed part in all instructions //of the first part of FB1
         case(op)
 //ADD Instruction in Enqueue Phase
           3'b000: begin
                    {rB, space, rC} = fb1[17:8] ; //This part is //differ from instruction to other 
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                      end
                     else
                      begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                      end
                    end
                
                   if (!reg_file_flag[rC])
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = rC ;
                    end
                    enqu_bus_buff_odd = {fb1[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
                   end
 //ADDI Instruction in Enqueue Phase
           3'b001: begin
                    {rB, imm} = fb1[17:8] ; //This part is differ //from instruction to other  
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = rB ;
                      end
                    end
                    ID_C = 3'b0 ;   
                    reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                    enqu_bus_buff_odd = {fb1[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                   end
 //NAND Instruction in Enqueue Phase
           3'b010: begin
                     {rB, space, rC} = fb1[17:8] ;//This part is //differ from instruction to other 
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = rB ;
                      end
                    end
                 
                    if (!reg_file_flag[rC])
                     begin
                      reg_file_out2 = reg_file[rC] ;
                      ID_C = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out2 = reg_file[rC] ;
                      ID_C = rC ;
                     end
                    enqu_bus_buff_odd = {fb1[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
                   end
 //LUI Instruction in Enqueue Phase
           3'b011: begin
                    extend_imm = fb1[17:8] ;
                    ID_B = 3'b0 ;
                    ID_C = 3'b0 ;
                    reg_file_out1 = {extend_imm, 6'b0} ;
                    enqu_bus_buff_odd = {fb1[23:0], reg_file_out1, ID_B, 16'b0, ID_C} ; //Note that we discard the value of reg_file_out2
//The odd bus now is busy with the recent instruction so we do //the following
                  enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;
                  end                    
 //LW Instruction in Enqueue Phase 
           3'b100: begin
                    {rB, imm} = fb1[17:8] ; //This part is differ //from instruction to other  
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = rB ;
                      end
                    end
                    ID_C = 3'b0 ;   
                    reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                    enqu_bus_buff_odd = {fb1[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;
                    //The odd bus now is busy with the recent //instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                   end
 //SW Instruction in Enqueue Phase 
             3'b101: begin
                      {rB, imm} = fb1[17:8] ; //This part is differ //from instruction to other  
                      begin
                        if (!reg_file_flag[rA])
                         begin
                          reg_file_out2 = reg_file[rA] ;
                          ID_A = 3'b0 ;
                         end
                        else
                         begin
                          reg_file_out2 = reg_file[rA] ;
                          ID_A = rA ;
                         end
                       if (!reg_file_flag[rB])
                        begin
                         reg_file_out1 = reg_file[rB] ;
                         ID_B = 3'b0 ;
                        end
                       else
                        begin
                         reg_file_out1 = reg_file[rB] ;
                         ID_B = rB ;
                        end
                      end
                      ID_C = 3'b0 ;
                      reg_file_out2 = reg_file[rA] ;   
                      src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                      enqu_bus_buff_odd = {fb1[23:0],reg_file_out1, ID_B, src_operand, ID_A} ;
                      //The odd bus now is busy with the recent //instruction so we do the following
                      enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                     end
 //BEQ Instruction in Enqueue Phase 
           3'b110: begin
                     {rB, imm} = fb1[17:8] ; //This part is differ //from instruction to other
                     if (!reg_file_flag[rA])
                      begin
                       reg_file_out2 = reg_file[rA] ;
                       ID_A = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out2 = reg_file[rA] ;
                       ID_A = rA ;
                      end
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                    ID_C = 3'b0 ;
                    branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
                    enqu_bus_buff_odd = {fb1[23:0],reg_file_out1, ID_B, reg_file_out2, ID_A} ;//The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ; 
                   end
 //JALR Instruction in Enqueue Phase 
           3'b111: begin
                    {rB, imm} = fb1[17:8] ; //This part is differ //from instruction to other 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                    ID_C = 3'b0 ;
                    reg_file_out2 = 16'b0 ;
                    enqu_bus_buff_odd = {fb1[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;
                    //The odd bus now is busy with the recent //instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;                  
                    end                    
         endcase
       end
     end
       
///
else if (ff[1])
  begin

/////////////////////////////////////////////////////
//For the first half of the second Fetch buffer/////
///////////////////////////////////////////////////
  begin
    {op, rA} = fb2[47:42] ; //Fixed part in all instructions of the first part of FB1
    case(op)
//ADD Instruction in Enqueue Phase
      3'b000: begin
               {rB, space, rC} = fb2[41:32] ; //This part is differ //from instruction to other 
               begin 
                if (!reg_file_flag[rB])
                 begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = 3'b0 ;
                 end
                else
                 begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = rB ;
                 end
               end
           
              if (!reg_file_flag[rC])
               begin
                reg_file_out2 = reg_file[rC] ;
                ID_C = 3'b0 ;
               end
              else
               begin
                reg_file_out2 = reg_file[rC] ;
                ID_C = rC ;
               end
               enqu_bus_buff_even = {fb2[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
              end
//ADDI Instruction in Enqueue Phase
      3'b001: begin
               {rB, imm} = fb2[41:32] ;//This part is differ from //instruction to other  
               begin 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
               end
               ID_C = 3'b0 ;   
               reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
               enqu_bus_buff_even = {fb2[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;                                      
               end
//NAND Instruction in Enqueue Phase
      3'b010: begin
                {rB, space, rC} = fb2[41:32] ; //This part is //differ from instruction to other 
               begin 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
               end
            
               if (!reg_file_flag[rC])
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = 3'b0 ;
                end
               else
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = rC ;
                end
               enqu_bus_buff_even = {fb2[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
              end
//LUI Instruction in Enqueue Phase
      3'b011: begin
               extend_imm = fb2[41:32] ;
               ID_B = 3'b0 ;
               ID_C = 3'b0 ;
               reg_file_out1 = {extend_imm, 6'b0} ;
               enqu_bus_buff_even = {fb2[47:24], reg_file_out1, ID_B, 16'b0, ID_C} ; //Note that we discard the value of reg_file_out2
               //The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
              end
//LW Instruction in Enqueue Phase 
      3'b100: begin
               {rB, imm} = fb2[41:32] ; //This part is differ from //instruction to other  
               begin 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
               end
               ID_C = 3'b0 ;   
               reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
               enqu_bus_buff_even = {fb2[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
              end
//SW Instruction in Enqueue Phase 
        3'b101: begin
                 {rB, imm} = fb2[41:32] ; //This part is differ //from instruction to other  
                 begin
                   if (!reg_file_flag[rA])
                    begin
                     reg_file_out2 = reg_file[rA] ;
                     ID_A = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out2 = reg_file[rA] ;
                     ID_A = rA ;
                    end
                  if (!reg_file_flag[rB])
                   begin
                    reg_file_out1 = reg_file[rB] ;
                    ID_B = 3'b0 ;
                   end
                  else
                   begin
                    reg_file_out1 = reg_file[rB] ;
                    ID_B = rB ;
                   end
                 end
                 ID_C = 3'b0 ;
                 reg_file_out2 = reg_file[rA] ;   
                 src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                 enqu_bus_buff_even = {fb2[47:24],reg_file_out1, ID_B, src_operand, ID_A} ;//The even bus now is busy with the //recent instruction so we do the following
                 enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;  
                end
//BEQ Instruction in Enqueue Phase 
      3'b110: begin
                {rB, imm} = fb2[41:32] ; //This part is differ //from instruction to other
                if (!reg_file_flag[rA])
                 begin
                  reg_file_out2 = reg_file[rA] ;
                  ID_A = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out2 = reg_file[rA] ;
                  ID_A = rA ;
                 end
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                end
               else
                begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = rB ;
                end
               ID_C = 3'b0 ;
               branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
               enqu_bus_buff_even = {fb2[47:24],reg_file_out1, ID_B, reg_file_out2, ID_A} ;//The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
              end
//JALR Instruction in Enqueue Phase 
      3'b111: begin
               {rB, imm} = fb2[41:32] ; //This part is differ from //instruction to other 
               if (!reg_file_flag[rB])
                begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = 3'b0 ;
                end
               else
                begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = rB ;
                end
               ID_C = 3'b0 ;
               reg_file_out2 = 16'b0 ;
               enqu_bus_buff_even = {fb2[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;
              end
    endcase
  end











////////////////////////////////////////////////////////////
//for Second half of second Fetch buffer///////////////////
//////////////////////////////////////////////////////////
   begin
     {op, rA} = fb2[23:18] ; //Fixed part in all instructions of //the first part of FB1
     case(op)
//ADD Instruction in Enqueue Phase
       3'b000: begin
                {rB, space, rC} = fb1[17:8] ; //This part is differ //from instruction to other 
                begin 
                 if (!reg_file_flag[rB])
                  begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                  end
                 else
                  begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                  end
                end
            
               if (!reg_file_flag[rC])
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = 3'b0 ;
                end
               else
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = rC ;
                end
                enqu_bus_buff_odd = {fb2[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
               end
//ADDI Instruction in Enqueue Phase
       3'b001: begin
                {rB, imm} = fb2[17:8] ; //This part is differ from //instruction to other  
                begin 
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = rB ;
                  end
                end
                ID_C = 3'b0 ;   
                reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                enqu_bus_buff_odd = {fb2[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
               end
//NAND Instruction in Enqueue Phase
       3'b010: begin
                 {rB, space, rC} = fb2[17:8] ; //This part is //differ from instruction to other 
                begin 
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = rB ;
                  end
                end
             
                if (!reg_file_flag[rC])
                 begin
                  reg_file_out2 = reg_file[rC] ;
                  ID_C = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out2 = reg_file[rC] ;
                  ID_C = rC ;
                 end
                enqu_bus_buff_odd = {fb2[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
               end
//LUI Instruction in Enqueue Phase
       3'b011: begin
                extend_imm = fb2[17:8] ;
                ID_B = 3'b0 ;
                ID_C = 3'b0 ;
                reg_file_out1 = {extend_imm, 6'b0} ;
                enqu_bus_buff_odd = {fb2[23:0], reg_file_out1, ID_B, 16'b0, ID_C} ; //Note that we discard the value of reg_file_out2
//The odd bus now is busy with the recent instruction so we do //the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;
              end                    
//LW Instruction in Enqueue Phase 
       3'b100: begin
                {rB, imm} = fb2[17:8] ; //This part is differ from //instruction to other  
                begin 
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = rB ;
                  end
                end
                ID_C = 3'b0 ;   
                reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                enqu_bus_buff_odd = {fb2[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
               end
//SW Instruction in Enqueue Phase 
         3'b101: begin
                  {rB, imm} = fb2[17:8] ; //This part is differ //from instruction to other  
                  begin
                    if (!reg_file_flag[rA])
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = rA ;
                     end
                   if (!reg_file_flag[rB])
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                    end
                  end
                  ID_C = 3'b0 ;
                  reg_file_out2 = reg_file[rA] ;   
                  src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                  enqu_bus_buff_odd = {fb2[23:0],reg_file_out1, ID_B, src_operand, ID_A} ;//The odd bus now is busy with the recent //instruction so we do the following
                  enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                 end
//BEQ Instruction in Enqueue Phase 
       3'b110: begin
                 {rB, imm} = fb2[17:8] ; //This part is differ //from instruction to other
                 if (!reg_file_flag[rA])
                  begin
                   reg_file_out2 = reg_file[rA] ;
                   ID_A = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out2 = reg_file[rA] ;
                   ID_A = rA ;
                  end
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
                ID_C = 3'b0 ;
                branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
                enqu_bus_buff_odd = {fb2[23:0],reg_file_out1, ID_B, reg_file_out2, ID_A} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ; 
               end
//JALR Instruction in Enqueue Phase 
       3'b111: begin
                {rB, imm} = fb2[17:8] ; //This part is differ from //instruction to other 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
                ID_C = 3'b0 ;
                reg_file_out2 = 16'b0 ;
                enqu_bus_buff_odd = {fb2[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;                  
                end                    
     endcase
     end
    end
    else if (ff[2])
      begin







/////////////////////////////////////////////////////
//For the first half of the Third Fetch buffer//////
///////////////////////////////////////////////////
      begin
        {op, rA} = fb3[47:42] ; //Fixed part in all instructions //of the first part of FB1
        case(op)
//ADD Instruction in Enqueue Phase
          3'b000: begin
                   {rB, space, rC} = fb3[41:32] ; //This part is //differ from instruction to other 
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = 3'b0 ;
                     end
                    else
                     begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                     end
                   end
               
                  if (!reg_file_flag[rC])
                   begin
                    reg_file_out2 = reg_file[rC] ;
                    ID_C = 3'b0 ;
                   end
                  else
                   begin
                    reg_file_out2 = reg_file[rC] ;
                    ID_C = rC ;
                   end
                   enqu_bus_buff_even = {fb3[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
                  end
//ADDI Instruction in Enqueue Phase
          3'b001: begin
                   {rB, imm} = fb3[41:32] ; //This part is differ //from instruction to other  
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                   end
                   ID_C = 3'b0 ;   
                   reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                   enqu_bus_buff_even = {fb3[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;                                      
                   end
//NAND Instruction in Enqueue Phase
          3'b010: begin
                    {rB, space, rC} = fb3[41:32] ; //This part is //differ from instruction to other 
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                   end
                
                   if (!reg_file_flag[rC])
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = rC ;
                    end
                   enqu_bus_buff_even = {fb3[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;
//The even bus now is busy with the recent instruction so we //do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
                  end
//LUI Instruction in Enqueue Phase
          3'b011: begin
                   extend_imm = fb3[41:32] ;
                   ID_B = 3'b0 ;
                   ID_C = 3'b0 ;
                   reg_file_out1 = {extend_imm, 6'b0} ;
                   enqu_bus_buff_even = {fb1[47:24], reg_file_out1, ID_B, 16'b0, ID_C} ; //Note that we discard the value of //reg_file_out2
//The even bus now is busy with the recent instruction so we //do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
                  end
//LW Instruction in Enqueue Phase 
          3'b100: begin
                   {rB, imm} = fb3[41:32] ; //This part is differ //from instruction to other  
                   begin 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                   end
                   ID_C = 3'b0 ;   
                   reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                   enqu_bus_buff_even = {fb3[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
                  end
//SW Instruction in Enqueue Phase 
            3'b101: begin
                     {rB, imm} = fb3[41:32] ; //This part is differ //from instruction to other  
                     begin
                       if (!reg_file_flag[rA])
                        begin
                         reg_file_out2 = reg_file[rA] ;
                         ID_A = 3'b0 ;
                        end
                       else
                        begin
                         reg_file_out2 = reg_file[rA] ;
                         ID_A = rA ;
                        end
                      if (!reg_file_flag[rB])
                       begin
                        reg_file_out1 = reg_file[rB] ;
                        ID_B = 3'b0 ;
                       end
                      else
                       begin
                        reg_file_out1 = reg_file[rB] ;
                        ID_B = rB ;
                       end
                     end
                     ID_C = 3'b0 ;
                     reg_file_out2 = reg_file[rA] ;   
                     src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                     enqu_bus_buff_even = {fb3[47:24],reg_file_out1, ID_B, src_operand, ID_A} ; //The even bus now is busy with the //recent instruction so we do the following
                     enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;  
                    end
//BEQ Instruction in Enqueue Phase 
          3'b110: begin
                    {rB, imm} = fb3[41:32] ; //This part is differ //from instruction to other
                    if (!reg_file_flag[rA])
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = rA ;
                     end
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                    end
                   ID_C = 3'b0 ;
                   branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
                   enqu_bus_buff_even = {fb3[47:24],reg_file_out1, ID_B, reg_file_out2, ID_A} ; //The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
                  end
//JALR Instruction in Enqueue Phase 
          3'b111: begin
                   {rB, imm} = fb3[41:32] ; //This part is differ //from instruction to other 
                   if (!reg_file_flag[rB])
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                    end
                   ID_C = 3'b0 ;
                   reg_file_out2 = 16'b0 ;
                   enqu_bus_buff_even = {fb3[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the //recent instruction so we do the following
                   enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;
                  end
        endcase
      end








////////////////////////////////////////////////////////////
//for Second half of Third Fetch buffer////////////////////
//////////////////////////////////////////////////////////
       begin
         {op, rA} = fb3[23:18] ; //Fixed part in all instructions //of the first part of FB1
         case(op)
 //ADD Instruction in Enqueue Phase
           3'b000: begin
                    {rB, space, rC} = fb3[17:8] ; //This part is //differ from instruction to other 
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                      end
                     else
                      begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                      end
                    end
                
                   if (!reg_file_flag[rC])
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out2 = reg_file[rC] ;
                     ID_C = rC ;
                    end
                    enqu_bus_buff_odd = {fb3[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
                   end
 //ADDI Instruction in Enqueue Phase
           3'b001: begin
                    {rB, imm} = fb3[17:8] ; //This part is differ //from instruction to other  
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = rB ;
                      end
                    end
                    ID_C = 3'b0 ;   
                    reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                    enqu_bus_buff_odd = {fb3[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                   end
 //NAND Instruction in Enqueue Phase
           3'b010: begin
                     {rB, space, rC} = fb3[17:8] ; //This part is //differ from instruction to other 
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = rB ;
                      end
                    end
                 
                    if (!reg_file_flag[rC])
                     begin
                      reg_file_out2 = reg_file[rC] ;
                      ID_C = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out2 = reg_file[rC] ;
                      ID_C = rC ;
                     end
                    enqu_bus_buff_odd = {fb3[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
                   end
 //LUI Instruction in Enqueue Phase
           3'b011: begin
                    extend_imm = fb3[17:8] ;
                    ID_B = 3'b0 ;
                    ID_C = 3'b0 ;
                    reg_file_out1 = {extend_imm, 6'b0} ;
                    enqu_bus_buff_odd = {fb3[23:0], reg_file_out1, ID_B, 16'b0, ID_C} ; //Note that we discard the value of //reg_file_out2
//The odd bus now is busy with the recent instruction so we do //the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;
                  end                    
 //LW Instruction in Enqueue Phase 
           3'b100: begin
                    {rB, imm} = fb3[17:8] ; //This part is differ //from instruction to other  
                    begin 
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = rB ;
                      end
                    end
                    ID_C = 3'b0 ;   
                    reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                    enqu_bus_buff_odd = {fb3[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                   end
 //SW Instruction in Enqueue Phase 
             3'b101: begin
                      {rB, imm} = fb3[17:8] ; //This part is differ //from instruction to other  
                      begin
                        if (!reg_file_flag[rA])
                         begin
                          reg_file_out2 = reg_file[rA] ;
                          ID_A = 3'b0 ;
                         end
                        else
                         begin
                          reg_file_out2 = reg_file[rA] ;
                          ID_A = rA ;
                         end
                       if (!reg_file_flag[rB])
                        begin
                         reg_file_out1 = reg_file[rB] ;
                         ID_B = 3'b0 ;
                        end
                       else
                        begin
                         reg_file_out1 = reg_file[rB] ;
                         ID_B = rB ;
                        end
                      end
                      ID_C = 3'b0 ;
                      reg_file_out2 = reg_file[rA] ;   
                      src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                      enqu_bus_buff_odd = {fb3[23:0],reg_file_out1, ID_B, src_operand, ID_A} ;//The odd bus now is busy with the //recent instruction so we do the following
                      enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                     end
 //BEQ Instruction in Enqueue Phase 
           3'b110: begin
                     {rB, imm} = fb3[17:8] ; //This part is differ //from instruction to other
                     if (!reg_file_flag[rA])
                      begin
                       reg_file_out2 = reg_file[rA] ;
                       ID_A = 3'b0 ;
                      end
                     else
                      begin
                       reg_file_out2 = reg_file[rA] ;
                       ID_A = rA ;
                      end
                     if (!reg_file_flag[rB])
                      begin
                       reg_file_out1 = reg_file[rB] ;
                       ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                    ID_C = 3'b0 ;
                    branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
                    enqu_bus_buff_odd = {fb3[23:0],reg_file_out1, ID_B, reg_file_out2, ID_A} ; //The odd bus now is busy with the //recent instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ; 
                   end
 //JALR Instruction in Enqueue Phase 
           3'b111: begin
                    {rB, imm} = fb3[17:8] ; //This part is differ //from instruction to other 
                    if (!reg_file_flag[rB])
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out1 = reg_file[rB] ;
                      ID_B = rB ;
                     end
                    ID_C = 3'b0 ;
                    reg_file_out2 = 16'b0 ;
                    enqu_bus_buff_odd = {fb3[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;
                    //The odd bus now is busy with the recent //instruction so we do the following
                    enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;                  
                    end                    
         endcase
       end
     end
     else if (ff[3])
  begin





/////////////////////////////////////////////////////
//For the first half of the forth Fetch buffer//////
///////////////////////////////////////////////////
  begin
    {op, rA} = fb4[47:42] ; //Fixed part in all instructions of the first part of FB1
    case(op)
//ADD Instruction in Enqueue Phase
      3'b000: begin
               {rB, space, rC} = fb4[41:32] ; //This part is differ //from instruction to other 
               begin 
                if (!reg_file_flag[rB])
                 begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = 3'b0 ;
                 end
                else
                 begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = rB ;
                 end
               end
           
              if (!reg_file_flag[rC])
               begin
                reg_file_out2 = reg_file[rC] ;
                ID_C = 3'b0 ;
               end
              else
               begin
                reg_file_out2 = reg_file[rC] ;
                ID_C = rC ;
               end
               enqu_bus_buff_even = {fb4[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;
               //The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
              end
//ADDI Instruction in Enqueue Phase
      3'b001: begin
               {rB, imm} = fb4[41:32] ; //This part is differ from //instruction to other  
               begin 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
               end
               ID_C = 3'b0 ;   
               reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
               enqu_bus_buff_even = {fb4[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;                                      
               end
//NAND Instruction in Enqueue Phase
      3'b010: begin
                {rB, space, rC} = fb4[41:32] ; //This part is //differ from instruction to other 
               begin 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
               end
            
               if (!reg_file_flag[rC])
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = 3'b0 ;
                end
               else
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = rC ;
                end
               enqu_bus_buff_even = {fb4[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
              end
//LUI Instruction in Enqueue Phase
      3'b011: begin
               extend_imm = fb4[41:32] ;
               ID_B = 3'b0 ;
               ID_C = 3'b0 ;
               reg_file_out1 = {extend_imm, 6'b0} ;
               enqu_bus_buff_even = {fb4[47:24], reg_file_out1, ID_B, 16'b0, ID_C} ; //Note that we discard the value of reg_file_out2
//The even bus now is busy with the recent instruction so we //do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
              end
//LW Instruction in Enqueue Phase 
      3'b100: begin
               {rB, imm} = fb4[41:32] ; //This part is differ from //instruction to other  
               begin 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
               end
               ID_C = 3'b0 ;   
               reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
               enqu_bus_buff_even = {fb4[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The even bus now is busy with the recent //instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;   
              end
//SW Instruction in Enqueue Phase 
        3'b101: begin
                 {rB, imm} = fb4[41:32] ; //This part is differ //from instruction to other  
                 begin
                   if (!reg_file_flag[rA])
                    begin
                     reg_file_out2 = reg_file[rA] ;
                     ID_A = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out2 = reg_file[rA] ;
                     ID_A = rA ;
                    end
                  if (!reg_file_flag[rB])
                   begin
                    reg_file_out1 = reg_file[rB] ;
                    ID_B = 3'b0 ;
                   end
                  else
                   begin
                    reg_file_out1 = reg_file[rB] ;
                    ID_B = rB ;
                   end
                 end
                 ID_C = 3'b0 ;
                 reg_file_out2 = reg_file[rA] ;   
                 src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                 enqu_bus_buff_even = {fb4[47:24],reg_file_out1, ID_B, src_operand, ID_A} ;//The even bus now is busy with the //recent instruction so we do the following
                 enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;  
                end
//BEQ Instruction in Enqueue Phase 
      3'b110: begin
                {rB, imm} = fb4[41:32] ; //This part is differ //from instruction to other
                if (!reg_file_flag[rA])
                 begin
                  reg_file_out2 = reg_file[rA] ;
                  ID_A = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out2 = reg_file[rA] ;
                  ID_A = rA ;
                 end
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                end
               else
                begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = rB ;
                end
               ID_C = 3'b0 ;
               branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
               enqu_bus_buff_even = {fb4[47:24],reg_file_out1, ID_B, reg_file_out2, ID_A} ; //The even bus now is busy with the //recent instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ; 
              end
//JALR Instruction in Enqueue Phase 
      3'b111: begin
               {rB, imm} = fb4[41:32] ; //This part is differ from //instruction to other 
               if (!reg_file_flag[rB])
                begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = 3'b0 ;
                end
               else
                begin
                 reg_file_out1 = reg_file[rB] ;
                 ID_B = rB ;
                end
               ID_C = 3'b0 ;
               reg_file_out2 = 16'b0 ;
               enqu_bus_buff_even = {fb4[47:24],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The even bus now is busy with the //recent instruction so we do the following
               enqu_bus_buff_flag_even = {enqu_bus_buff_flag_even[0], enqu_bus_buff_flag_even[1]} ;
              end
    endcase
  end










////////////////////////////////////////////////////////////
//for Second half of fourth Fetch buffer////////////////////
//////////////////////////////////////////////////////////
   begin
     {op, rA} = fb4[23:18] ; //Fixed part in all instructions of //the first part of FB1
     case(op)
//ADD Instruction in Enqueue Phase
       3'b000: begin
                {rB, space, rC} = fb4[17:8] ; //This part is differ //from instruction to other 
                begin 
                 if (!reg_file_flag[rB])
                  begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                  end
                 else
                  begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                  end
                end
            
               if (!reg_file_flag[rC])
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = 3'b0 ;
                end
               else
                begin
                 reg_file_out2 = reg_file[rC] ;
                 ID_C = rC ;
                end
                enqu_bus_buff_odd = {fb4[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
               end
//ADDI Instruction in Enqueue Phase
       3'b001: begin
                {rB, imm} = fb4[17:8] ; //This part is differ from //instruction to other  
                begin 
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = rB ;
                  end
                end
                ID_C = 3'b0 ;   
                reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                enqu_bus_buff_odd = {fb4[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
               end
//NAND Instruction in Enqueue Phase
       3'b010: begin
                 {rB, space, rC} = fb4[17:8] ; //This part is //differ from instruction to other 
                begin 
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = rB ;
                  end
                end
             
                if (!reg_file_flag[rC])
                 begin
                  reg_file_out2 = reg_file[rC] ;
                  ID_C = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out2 = reg_file[rC] ;
                  ID_C = rC ;
                 end
                enqu_bus_buff_odd = {fb4[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;  
               end
//LUI Instruction in Enqueue Phase
       3'b011: begin
                extend_imm = fb4[17:8] ;
                ID_B = 3'b0 ;
                ID_C = 3'b0 ;
                reg_file_out1 = {extend_imm, 6'b0} ;
                enqu_bus_buff_odd = {fb4[23:0], reg_file_out1, ID_B, 16'b0, ID_C} ; //Note that we discard the value of reg_file_out2
//The odd bus now is busy with the recent instruction so we do //the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;
              end                    
//LW Instruction in Enqueue Phase 
       3'b100: begin
                {rB, imm} = fb4[17:8] ; //This part is differ from //instruction to other  
                begin 
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = rB ;
                  end
                end
                ID_C = 3'b0 ;   
                reg_file_out2 = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                enqu_bus_buff_odd = {fb4[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ;//The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
               end
//SW Instruction in Enqueue Phase 
         3'b101: begin
                  {rB, imm} = fb4[17:8] ; //This part is differ //from instruction to other  
                  begin
                    if (!reg_file_flag[rA])
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = 3'b0 ;
                     end
                    else
                     begin
                      reg_file_out2 = reg_file[rA] ;
                      ID_A = rA ;
                     end
                   if (!reg_file_flag[rB])
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = 3'b0 ;
                    end
                   else
                    begin
                     reg_file_out1 = reg_file[rB] ;
                     ID_B = rB ;
                    end
                  end
                  ID_C = 3'b0 ;
                  reg_file_out2 = reg_file[rA] ;   
                  src_operand = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};          
                  enqu_bus_buff_odd = {fb4[23:0],reg_file_out1, ID_B, src_operand, ID_A} ;
                  //The odd bus now is busy with the recent //instruction so we do the following
                  enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;   
                 end
//BEQ Instruction in Enqueue Phase 
       3'b110: begin
                 {rB, imm} = fb4[17:8] ; //This part is differ //from instruction to other
                 if (!reg_file_flag[rA])
                  begin
                   reg_file_out2 = reg_file[rA] ;
                   ID_A = 3'b0 ;
                  end
                 else
                  begin
                   reg_file_out2 = reg_file[rA] ;
                   ID_A = rA ;
                  end
                 if (!reg_file_flag[rB])
                  begin
                   reg_file_out1 = reg_file[rB] ;
                   ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
                ID_C = 3'b0 ;
                branch_count_cntl = imm[6]?{9'b111111111,imm}:{9'b000000000,imm};
                enqu_bus_buff_odd = {fb4[23:0],reg_file_out1, ID_B, reg_file_out2, ID_A} ; //The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ; 
               end
//JALR Instruction in Enqueue Phase 
       3'b111: begin
                {rB, imm} = fb4[17:8] ; //This part is differ from //instruction to other 
                if (!reg_file_flag[rB])
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = 3'b0 ;
                 end
                else
                 begin
                  reg_file_out1 = reg_file[rB] ;
                  ID_B = rB ;
                 end
                ID_C = 3'b0 ;
                reg_file_out2 = 16'b0 ;
                enqu_bus_buff_odd = {fb4[23:0],reg_file_out1, ID_B, reg_file_out2, ID_C} ; //The odd bus now is busy with the recent //instruction so we do the following
                enqu_bus_buff_flag_odd = {enqu_bus_buff_flag_odd[0], enqu_bus_buff_flag_odd[1]} ;                  
                end                    
     endcase
   end
  end
end






//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//Enqeue phase (end)//////////////////////////////////////////
/////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////
else // if not enable turn on waiting LED
  waiting = 1'b1 ;
end

//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
//Issue phase (start)/////////////////////////////////////////
/////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////
reg [61:0]IQ0,IQ1,IQ2,IQ3,IQ4,IQ5,IQ6,IQ7 ; //Instruction Queue registers
reg [7:0]IQ_check ; // This register check if the IQ register is //empty or not
reg [7:0]issue ; //Issue register that check if the instruction is ready to be executed or not
//islot x check which ALU which the instruction will be //destinated
reg [1:0]islot0, islot1, islot2, islot3, islot4, islot5, islot6, islot7 ;


always @(posedge clk)

 begin
   if (en) //Processor enable
     begin
       if (!reset)
         begin // reset all vectors
           IQ_check = 8'b0 ;
           issue = 8'b0 ;
           islot0 = 2'b0 ; islot1 = 2'b0 ; islot2 = 2'b0 ;
           islot3 = 2'b0 ; islot4 = 2'b0 ; islot5 = 2'b0 ;
           islot6 = 2'b0 ; islot7 = 2'b0 ;
           bus_check_even = 1'b0;
           bus_check_odd = 1'b0 ;
         end
       else
         begin
         if (enqu_bus_buff_flag_even) //checking even bus
           begin
             if (!IQ_check[0])
               begin
                 IQ0 = enqu_bus_buff_even ;
                 bus_check_even = 1'b0 ; //bus empty
                 IQ_check[0] = 1'b1 ; 
                 out_data = ff[0];
               end
           end
         end
       
       end
     end
        
endmodule
