// Add, Compare and Select
module ACS(clk, reset, h00, h01, h10, h11, data_out);

  output [3:0] data_out;
  input  [3:0] h00, h01, h10, h11;
  input  clk, reset;
  
  reg [3:0] data_out;
  reg [3:0] H00, H01, H10, H11;
  reg [3:0] H00nxt, H01nxt, H10nxt, H11nxt;

  always @ (posedge clk)
  begin
  if(!reset)  // Initially reseting all registers.
  begin
  data_out = 4'b0;
  
  H00 = 4'b0000;  H01 = 4'b0011;
  H10 = 4'b0101;  H11 = 4'b0111;
  
  H00nxt = 4'b0000;   H01nxt = 4'b0000;
  H10nxt = 4'b0000;   H11nxt = 4'b0000;
  end
  
  else 
  begin
  if (H00+h00 > H01+h11) 
  H00nxt = H01 + h11;
  
  else if (H00+h11 > H01+h00)
  H10nxt = H01 + h00;
  
  else if (H10+h10 > H11+h01)
  H01nxt = H11 + h01;
  
  else if (H10+h01 > H11+h10)  
  H11nxt = H11 + h10;
  
  else
  begin
    H00nxt = H00 + h00;
    H10nxt = H00 + h11;
    H01nxt = H10 + h10;
    H11nxt = H10 + h01;
    
    H00 <= H00nxt;
    H01 <= H01nxt;
    H10 <= H10nxt;
    H11 <= H11nxt;
  end
  end
  end
endmodule
