APS-X84 VHDL/FPGA SYNTHESIS TUTORIAL

VHDL/FPGA LAB #3
LATCHED AND GATE

In this LAB we will add to the AND gate program (LAB #1) and LATCH the output with a newly created input pin we will call CLK. A basic functional block diagram is shown below: Additions are shown to our program in RED. A SIGNAL is added here because the WAIT statement operates on SIGNALS only. As can be seen in the ARCHITECTURE the SIGNAL SCLK connects right to the CLK entity element whose ATTRIBUTE is pin five of the FPGA. This allows us to control the clock via one of our 8255 pins on the X84 board.

library IEEE; use IEEE.std_logic_1164.all; library METAMOR; use METAMOR.attributes.all; library SYNOPSYS; use SYNOPSYS.std_logic_arith.all; use SYNOPSYS.std_logic_unsigned.all; -- -- Begin Entity (This is a comment) -- ENTITY ANDGATE IS PORT ( Ain: in STD_LOGIC; Bin: in STD_LOGIC ; CLK: in STD_LOGIC; COut: out STD_LOGIC ); ATTRIBUTE pinnum of COut: signal is "P35"; ATTRIBUTE pinnum of Ain: signal is "P3"; ATTRIBUTE pinnum of Bin: signal is "P4"; ATTRIBUTE pinnum of CLK: signal is "P5"; END ANDGATE; -- -- Begin Architecture (This is a comment) -- ARCHITECTURE behave OF ANDGATE IS SIGNAL SCLK: STD_LOGIC; BEGIN SCLK <= CLK; CLK: PROCESS begin WAIT UNTIL SCLK'EVENT AND SCLK='1'; COut <= Ain AND Bin; end process; END behave;

Click HERE if you wish to return to the AND GATE lab to refamiliarize yourself with the following processes:

1) Open the X84Lab3 project in the Foundation Software projects.

2) Insure the project has been properly synthesized and routed.

3) Insure the X84Lab3.rbt file from the latest route version is stored in the X84Lab3C directory where the X84Lab3.exe file is located.

4) Execute the X84Lab3.exe program and you should see the following screen:

In this control program the AND gate on board updates its output, but the boards output LED only responds after options 5 and six are selected, thus setting the clock low then high, simulating a rising edge on the clock line.