APS-X84 VHDL/FPGA SYNTHESIS TUTORIAL

VHDL DATA TYPES

There are many data types which can be used in VHDL. To keep to the concept of this Lab book we will restrict ourselves to the following types for our discussions:

- SIGNAL
- CONSTANT
- VARIABLE

SIGNALs : A SIGNAL can be thought of as basically just a wire or bus which connects ENTITIES or logic with a design. SIGNALS are part of an ARCHITECTURE and are declared before the BEGIN statement, but after the ARCHITECTURE IS statement.. SIGNALS are what are called SCHEDULED elements. That is to say that they can be scheduled to occur on particular CLOCK edges. This will become more clear in our PROCESS section.

Example:

SIGNAL Count: INTEGER RANGE 0 TO 255;

CONSTANTs are declared in the same location and can be INTEGERS or STD_LOGIC or any other VHDL types. They are fixed values usually used for comparison purposes. the := OPERATOR is used to assign the CONSTANT value.

Example:

CONSTANT Multiplier : INTEGER RANGE 0 to 255 := 10;

VARIABLEs are values which can be of any data types but are used inside of PROCESSes. Their scope is tied to that process, and they are not SCHEDULED elements like SIGNALS are. That is to say that within the PROCESS which they are declared, the assignments/changes are immediately updated. This will become more clear after the discussion of PROCESSes.

Example:

VARIABLE MyVariable : INTEGER RANGE 7 DOWNTO 0;

Upon examination of the code below we see highlighted two statements which declare SIGNALS (BASICALLY INTERNAL WIRES) which are
INTEGERS in the range of 0 to 255 or 256 values. This INTEGER could be represented by 8 bits since 2^8 is equal to 256. By having the COUNT and MultCnt declared as INTEGERS we can more easily add and subtract counts.

We also see an INTEGER we named Multiplier which is not a SIGNAL but is in fact a CONSTANT. This is exactly what it sounds like. The format for the CONSTANT is the same as the SIGNAL format except the := sign is used to assign the CONSTANT value. This value will be STATIC and can be assigned or manipulated throughout the code. In our example we use the value to set a CONSTANT Multiplier which sets is used for comparison in an IF THEN condition statement.

library IEEE; use IEEE.std_logic_1164.all; library METAMOR; use METAMOR.attributes.all; library SYNOPSYS; use SYNOPSYS.std_logic_arith.all; use SYNOPSYS.std_logic_unsigned.all; library PN_PAK; use PN_PAK.PN_PAK.all; ENTITY X84DEMO IS PORT ( The555In: IN std_logic; DivSigOut: BUFFER std_logic; DivCntIn: IN std_logic_vector(7 downto 0) ); attribute pinnum of DivCntIn : signal is "P10,P9,P8,P7,P6,P5,P4,P3"; attribute pinnum of DivSigOut : signal is "P35"; attribute pinnum of The555In : signal is "P24"; END X84DEMO; ---------------------------------------------------------------- ---------------------------------------------------------------- ARCHITECTURE behave OF X84DEMO IS SIGNAL Count: INTEGER RANGE 0 TO 255; SIGNAL MultCnt: INTEGER RANGE 0 TO 255; -- Divide input by Multiplier times the DivCntIn value CONSTANT Multiplier : INTEGER RANGE 0 to 255 := 10; BEGIN DIVIDER: PROCESS BEGIN WAIT UNTIL The555In'EVENT AND The555In = '1'; -- wait til rising edge IF MultCnt >= Multiplier THEN Count <= Count +1; -- increment counter MultCnt <= 0; -- reinitialize Multiplier Counter ELSE MultCnt <= MultCnt + 1; -- Output divided pulse; END IF; IF Count >= slvect2int(DivCntIn,8) THEN DivSigOut <= NOT DivSigOut; -- toggle LED on X84 Count <= 0; -- reinitialize counter END IF; END PROCESS; END behave;