APS-X84 VHDL/FPGA SYNTHESIS TUTORIAL

THE VHDL PROCESS

Although hardware is concurrent (things happen simultaneously), VHDL allows you to implement algorithms with a series of sequential statements that occur inside what is called a PROCESS. Understanding the operation of PROCESSes is critical to understanding how VHDL synthesizes synchronous designs. A PROCESS is a CONCURRENT statement used in an architecture which requires a WAIT statement or SENSITIVITY list.

A SENSITIVITY list is a list of variables which if a change in them occur, will trigger the associated PROCESS. Inside of the PROCESS statements execute sequentially. That is to say, that they execute in order, like a standard programming language does.

An example of a SENSITIVITY LIST PROCESS

PROCESS (my_set, my_reset) begin if my_set = '1' then My_Output <= '1'; elsif my_reset = '1' then My_Output <= '0'; end process;

Any change in the my_set or my_reset will trigger the PROCESS to run. Let us reexamine our AND GATE example except this one will use a process with the two inputs Ain and Bin being on a sensitivity list.

library IEEE; use IEEE.std_logic_1164.all; library METAMOR; use METAMOR.attributes.all; library SYNOPSYS; use SYNOPSYS.std_logic_arith.all; use SYNOPSYS.std_logic_unsigned.all; -- -- Begin Entity (This is a comment) -- ENTITY ANDGATE IS PORT ( Ain: in STD_LOGIC; Bin: in STD_LOGIC ; COut: out STD_LOGIC ); ATTRIBUTE pinnum of COut: signal is "P35"; ATTRIBUTE pinnum of Ain: signal is "P3"; ATTRIBUTE pinnum of Bin: signal is "P2"; END ANDGATE; -- -- Begin Architecture (This is a comment) -- ARCHITECTURE behave OF ANDGATE IS BEGIN PROCESS (Ain, Bin) begin COut <= Ain AND Bin; end process; END behave;

This operation is eqivalent logically, but it wouldn't make much sense to do this since it adds a measure of complexity which is unneeded. The process sits there until either Ain or Bin change, then does what ever is inside of its begin and end process statements. The fact that all we have is the original AND expression does not discount the fact that we could put many other statements there.

Using a WAIT UNTIL statement is another way of implementing a PROCESS which is commonly used to simulated an edge triggered device. For SIGNALS which are changed in the PROCESS the changes are SCHEDULED. That is to say, the changes that occur within the PROCESS are reflected on the output of the associated SIGNAL on the next occurrence of the condition specified in a WAIT UNTIL statement.In the next piece of code we add an input clock line and use a WAIT UNTIL statement in the PROCESS as shown:

library IEEE; use IEEE.std_logic_1164.all; library METAMOR; use METAMOR.attributes.all; library SYNOPSYS; use SYNOPSYS.std_logic_arith.all; use SYNOPSYS.std_logic_unsigned.all; -- -- Begin Entity (This is a comment) -- ENTITY ANDGATE IS PORT ( Ain: in STD_LOGIC; Bin: in STD_LOGIC ; CLK: in STD_LOGIC; COut: out STD_LOGIC ); ATTRIBUTE pinnum of COut: signal is "P35"; ATTRIBUTE pinnum of Ain: signal is "P3"; ATTRIBUTE pinnum of Bin: signal is "P2"; END ANDGATE; -- -- Begin Architecture (This is a comment) -- ARCHITECTURE behave OF ANDGATE IS BEGIN CLK: PROCESS begin WAIT UNTIL CLK'EVENT AND CLK='1'; COut <= Ain AND Bin; end process; END behave;

This code now does not update COut until a rising edge is seen on the CLK line. This is essentially the following circuit

The statements inside the PROCESS occur on the NEXT clock edge. This can be thought of as a LATCHED vs. COMBINATORIAL processes. Combinatorial functions like AND/OR/XOR occur essentially immediately. While logic which is LATCHED does not become apparent until the CLOCK latches it out. And so in the statement A <= B which occurs outside a process, A essentially changes exactly as B does. However when placed inside a process with a WAIT UNTIL statement A will not reflect the change in B until the next WAIT UNTIL event (CLOCK) occurs.