APS-X84 VHDL/FPGA SYNTHESIS TUTORIAL

FPGA BASICS

GENERAL

PROGRAMMABLE DEVICES

A programmable logic device is a device whose logic characteristics can be changed and manipulated or stored through programming. The most common simple device which falls into this category is the PAL(Programmable Array Logic). The internals of simple PALs consist simply of an array of AND gates and an array of OR gates. The AND array is programmable while the OR array is relatively fixed. A switch matrix selects which of the PALs inputs will be connected to the AND inputs which are then connect to the fixed OR matrix. The outputs can often times be rerouted to the input matrixes. The 22V10 became a commonly used PAL device. A CPLD(Complex Programmable logic devices) is a device made of of smaller common macro cells (like a 22v10) which are programmably interconnected. Today's CPLDs can get quite large. Many companies produce CPLDs. AMD, Lattice, XILINX, and Cypress are just a few that come to mind.

FPGAs (Field Programmable Gate Arrays) are arrays of logic blocks which can be linked together to form complex logic implementations.A bit more flexible and complex than CPLDs and PALs, FPGAs can be separated into two categories; Fine Grained and Coarse grained. Fine grained being made up of a sea of gates or transistors or small macro cells , while coarse grained being made up of bigger macro cells which are often made up of flip flops and Look up Tables (LUTs) which make up the combinatorial logic functions. Inside the macro cell are often switches or multiplexers which allow for differing uses of the macro cell. The individual macro cells are connected together with a combination of switch matrixes and metal line matrixes which can be implemented with pass transistors, fuses/antifuses or multiplexers. The internal make up of the FPGAs can also be categorized by the technology implementation used. Several of those categories are:

PROM/EPROM/EEPROM/FLASH based - These are typically programmed out of circuit and can or cannot be reprogrammed [ E (erasable), EE(Electrically Erasable), PROM (one time programmable) ].

Anti-Fuse/Fuse based - Like proms are one time programmable.Fuses are permanently put in place. The obvious disadvantage is reuse, while the advantage often comes in size and cost.

Static Ram based- SRAM cells are implemented as function generators to simulate combinatorial logic and also are used to control muxs and routing resources. these are by far the most popular. These are also the type in the XILINX 4000/5000 series FPGAs which we will use in our LABs.

The FPGAs we will be considering for this text will be primarily XILINX SRAM based FPGAs. The basic building blocks for XILINX FPGAs are shown below:

XILINX CLB

The basic cell (called a CLB for Combinatorial Logic Block) is made up of three Function Generators (F,G,H). The F and G Generators are basically just RAM blocks with four address bits and one data bit. (basically a 16x 1 Ram which stores the combinatorial behavior of the given inputs. The H function generator has three inputs (F's output, G's output and a third input from outside the logic block. The CLB can implement functions of upto nine variables with this arrangement. In addition two flip flops are available which can store the function generators outputs. The architecture allows the Flip Flops to be used independently (Din) and has Set Reset circuitry . The outputs are Y, YQ, X and XQ. As can be seen, X can output F or H outputs and Y can output G or H outputs.

XILINX INPUT OUTPUT BLOCK

Now let us examine the XILINX Input/Output Block (IOB). The IOBs are how the FPGA interfaces to its pins or pads. I1 and I2 bring in signals from outside the FPGA. As can be seen each IOB has an input and output flip flop and an input and output buffer. Other features of the IOB to remember are:

- Inputs can be delayed by several nano-seconds to compensate for clock delays
- Outputs can be inverted or not.
- Buffers can be bypassed to eliminate delay.

Programmable Interconnects

All internal connections are made up of metal segments with programmable switching points to implement the routing. There are three main interconnect types:

Single Length Lines - a grid of horizontal and vertical lines which intersect at a switch matrix between each CLB.

Double Length Lines - a grid of horizontal and vertical lines which intersect at the switch matrixes between TWO CLBs.

Long Lines - form a grid of metal interconnection segments that run the entire length or width of the array. Global buffers can drive additional vertical lines designed to distribute clock signals and other high fanout signals

All these elements are used by the router/fitter software, to take your synthesized design and place it in the desired FPGA part. Understanding the architecture of an FPGA is very important when optimizing designs. We will not focus too heavily on this here, as this is an introductory text. More details can be found in the XILINX data book.