APS-X84 VHDL/FPGA SYNTHESIS TUTORIAL

LAB #5
Bringing Out Test Points

In this Lab we wil use our Counter timer example from LAB 4 and will bring out test points to some of the unused X84 boards FPGA pins. We will use a Logic Analyzer which connects up to the PC serial port called the PODALYZER from BOULDER CREEK ENGINEERING. The PODALYZER is available from APS in our advanced X84 kits.

We will measure and display the COUNTER test points by connecting up the PODALYZER to pins on the four X84 20 pin IDC connectors available on the top of the X84 card. First let us modify the VHDL code to tie relevant test points to the X84 board FPGA pins. By referencing the schematics (which comes with the X84 board kits) we choose FPGA pins which are free. For this example we will try to choose all our test points so that they all are contained in one of the X84 boards 20 pin connectors.By examining the pins we are already using in the counter example (shown in the text below) we see that the following pins are used.

attribute pinnum of DivCntIn : signal is "P10,P9,P8,P7,P6,P5,P4,P3"; attribute pinnum of DivSigOut : signal is "P35"; attribute pinnum of The555In : signal is "P24";

P10,P9,P8,P7,P6,P5,P4,P3,P24 Are all on X84 board J1
and P35 is on X84 board J2

So we will use J3 as our test connector. We could still use the other Test connectors and indeed could monitor the actual IO pins if we wanted, but for this lab we will bring out some signals which were invisible to the original design's IO pins.

J3's test pin connections to the Pod-Alyzer (or any other Logic Analyzer) are shown below:

X84 Board J3P2 (FPGA Pin 81) to POD-Alyzer CH0
X84 Board J3P3 (FPGA Pin 56) to POD-Alyzer CH1
X84 Board J3P4 (FPGA Pin 57) to POD-Alyzer CH2
X84 Board J3P5 (FPGA Pin 58) to POD-Alyzer CH3
X84 Board J3P6 (FPGA Pin 58) to POD-Alyzer CH4
X84 Board J3P7 (FPGA Pin 60) to POD-Alyzer CH5
X84 Board J3P8 (FPGA Pin 61) to POD-Alyzer CH6
X84 Board J3P9 (FPGA Pin 62) to POD-Alyzer CH7
X84 Board J3P10 (FPGA Pin 65) to POD-Alyzer CH8

Our new VHDL code with our new test points is shown below. The new code is highlighted. We will monitor the test count and be able to watch the output signal which controlled the LED toggle at the set term count.

library IEEE; use IEEE.std_logic_1164.all; library METAMOR; use METAMOR.attributes.all; library SYNOPSYS; use SYNOPSYS.std_logic_arith.all; use SYNOPSYS.std_logic_unsigned.all; library PN_PAK; use PN_PAK.PN_PAK.all; ENTITY X84DEMO IS PORT ( The555In: IN std_logic; DivSigOut: BUFFER std_logic; DivCntIn: IN std_logic_vector(7 downto 0); TestCount: OUT std_logic_vector(7 downto 0); -- new test points TestOut: OUT std_logic; -- new test points ); attribute pinnum of DivCntIn : signal is "P10,P9,P8,P7,P6,P5,P4,P3"; attribute pinnum of DivSigOut : signal is "P35"; attribute pinnum of The555In : signal is "P24"; attribute pinnum of TestCount : signal is "P62,P61,P60,P59,P58,P57,P56,P81"; attribute pinnum of TestOut : signal is "P65"; END X84DEMO; ---------------------------------------------------------------- ---------------------------------------------------------------- ARCHITECTURE behave OF X84DEMO IS SIGNAL Count: INTEGER RANGE 0 TO 255; SIGNAL MultCnt: INTEGER RANGE 0 TO 255; -- Divide input by Multiplier times the DivCntIn value CONSTANT Multiplier : INTEGER RANGE 0 to 255 := 10; BEGIN TestOut <= DivSigOut; -- output test clock TestCount <= int2slvect(Count,8); -- output test count DIVIDER: PROCESS BEGIN WAIT UNTIL The555In'EVENT AND The555In = '1'; -- wait til rising edge IF MultCnt >= Multiplier THEN Count <= Count +1; -- increment counter MultCnt <= 0; -- reinitialize Multiplier Counter ELSE MultCnt <= MultCnt + 1; -- Output divided pulse; END IF; IF Count >= slvect2int(DivCntIn) THEN DivSigOut <= NOT DivSigOut; -- toggle LED on X84 Count <= 0; -- reinitialize counter END IF; END PROCESS; END behave;

Click HERE if you wish to return to the AND GATE (lab #1) to refamiliarize yourself with the following processes:

1) Open the X84Lab5 project in the Foundation Software projects.

2) Insure the project has been properly synthesized and routed.

3) Insure the X84Lab5.rbt file from the latest route version is stored in the X84Lab5C directory where the X84Lab5C.exe file is located.

4) Execute the X84Lab5C.exe program and you should see the following screen:

By setting the divider value to 255 on the X84 LAB 5 screen, and triggering on the TestOut signal's positive edge the Pod-Alyzers display should be as shown:

The Pod-Alyzer enables us to convert Test Count into a Bus signal which we will view as an unsigned decimal. The new display should appear as shown below:

The Pod-Alyzer is a powerful tool. We have only used a small portion of its abilities in this Lab. Demo software is available which will show the full capabilities of the Pod-Alyzer. See the APS website or Boulder Creek Engineering for more details.

This is the end of the Simple X84 Lab examples. The advanced X84 Lab examples are not currently available on the website. They include:

- A programmable PN Generator
- A Matched Filter Pattern Correlator
- A Programmable Bit Error Rate Tester

Each application oriented example or Lab will be turn your X84 board into a useable device. A windows control program will be developed so that the programmable parameters for the board are easily set. So far the PN Generator and BERT tester will become such applications. Keep in touch with us on our website, and subscribe to our free Newsletter to keep yourself posted on the new X84 files!